In the design of a computer, the system aspect of the computer, i.e., computer architecture is typically designed first. Then the design of logic networks follows. Then transistor circuits are designed and laid out on integrated circuit chips. In this design sequence, if logic networks with a large number of logic gates are to be designed, manual design is not efficient because of excessively long design time, many design mistakes, and other reasons. Thus, logic networks that require a large number of logic gates are designed increasingly often by a logic synthesizer, i.e., a computer program for automated logic network design. After a logic network is synthesized, a transistor circuit based on this logic network is designed, typically using a cell library. This conversion from the logic network to the transistor circuit is called technology mapping. Then the transistor circuit is laid out on an integrated circuit chip. When designers have a layout, they usually discover problems that they could not foresee at the time of design of the logic network. As examples, some connections may be too long with excessive delay time, some logic gates are erroneously designed, some buffers need to be added, some of the network output functions need to be changed due to specification changes, or some others need to be changed. These problems have to be corrected. The changes for the corrections are called engineering changes. Another example of the occasions that necessitate engineering changes is a modification of old transistor circuits. Designers know that some old transistor circuits that they have used for some time work very reliably with good performance and have already some manufacturing setup. They want to use them with partial changes. Thus, they need engineering changes.
Many of these engineering changes have to be done by changing the original logic network, though some others can be done by directly changing the transistor circuit. In this case, some connections and/or gates in the original logic network are changed or deleted (some of the network output functions may be consequently changed), but designers do not want to change some portion of the original logic network because they already spent a lot of time in making layout and delay time calculation on the corresponding portion of the transistor circuit. Thus, from the original logic network, the designer wants to synthesize a new logic network, by keeping some portion of the original logic network unchanged and by redesigning the remaining portion of the network to recover the changed network output functions to the original network output functions.